Embedded processors may include a digital signal processor, a microcontroller, one or more DMA controllers and memory on a single integrated circuit chip. The performance of the embedded processor is largely determined by the associated memory system and, in particular, by a memory system that is external to the processor chip.
In an embedded system application, memory management is a critical part of developing a high performance system. In particular, because the data buffers and the instruction code are often too large to fit within internal memory, care must be taken in placing code and data to achieve the best performance. When an external memory, such as DDR SDRAM (double data rate synchronous dynamic random access memory) is used in a system, there are many factors that can negatively impact performance. As an example, accesses to inactive rows within DDR SDRAM require a row activation command by the external bus controller, which takes multiple memory clocks to execute. There are further performance penalties if consecutive accesses are made to different rows in the same internal bank of a SDRAM, in which case the controller must first deactivate the current row before it can activate the new row. If the external bus controller can keep track of rows in external memory that have been already activated, excessive row activation commands and the corresponding extra clock cycles can be avoided. Also, because of latencies associated with consecutive read and write accesses on the external bus, intermixing accesses can result in slower performance than accessing data in a more pipelined fashion.
Currently, there is no good way for a programmer to monitor what is happening in an application being executed on hardware. While simulation tools may exist, there is no good way to profile the activity at the external buses as reads and writes are made by the DMA controller and the core. As a result, programmers are forced into a trial and error method of moving data and code within external memory in search of the best performance.